1. Field
Example embodiments relate to semiconductor memory devices. Other example embodiments relate to semiconductor memory devices having strapping contacts in a strapping region with an increased pitch.
2. Description of the Related Art
Semiconductor memory devices may be classified as volatile memory devices (e.g., DRAM), in which all data stored in a memory cell is erased if a power source is turned off, or as non-volatile memory devices, in which data is preserved after a power source is turned off. Non-volatile memory devices include a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a phase-change random access memory (PRAM), a resistor random access memory (RRAM) and the like.
Among the non-volatile memory devices, the PRAM is a memory device using a phase-change material. The phase-change material refers to a material (e.g., chalcogenide) in which a phase varies with temperature and resistance varies with the phase. An alloy material (e.g., GexSbyTez(GST)) may be used as the phase-change material. The phase-change material may rapidly transform (or change) into one of two types of phases (e.g., amorphous and crystalline states) depending on a temperature. The phase-change material is in a high-resistance state in the amorphous state and in a low-resistance state in the crystalline state. As such, the phase-change material may be used as a semiconductor memory device, for example, by defining the high-resistance state as “reset” or logic “1” and defining the low-resistance state as “set” or logic “0.”
Memory cells constituting PRAM may be classified into memory cells having transistor and diode structures. The memory cell having a transistor structure may be a memory cell in which a phase-change material layer and a transistor are connected in series to each other. The memory cell having a diode structure may be a memory cell in which a phase-change material layer and a diode are connected in series to each other. The memory cell having a diode structure may have higher integration, higher speed and/or lower power characteristics compared with the memory cell having a transistor structure.
As the integration density of a memory device increases, the cross section of a word line gradually decreases and the length of the word line gradually increases, increasing the resistance of the word line. As such, in a PRAM, a delay exists on a word line when the word line is selected.
A method of applying a uniform voltage to memory cells array on a word line having strapping contacts to prevent a voltage drop due to the increased resistance of the word line has been acknowledged. In the method, a contact margin (or pitch) between adjacent strapping contacts may be reduced as the integration density of a memory device is increased. As such, a bridge or the like may occur.
FIG. 1 is a photograph showing a bridge phenomenon between strapping contacts arrayed in a strapping region of a conventional semiconductor memory device.
As shown in FIG. 1, a bridge is formed between adjacent strapping contacts 11 in the strapping region.